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[rv_plic] add missing output known assertion #728

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Merged
marnovandermaas merged 1 commit into from
Sep 16, 2026
Merged

[rv_plic] add missing output known assertion #728

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1 change: 1 addition & 0 deletions hw/top_chip/ip_autogen/rv_plic/rtl/rv_plic.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -276,6 +276,7 @@ module rv_plic import rv_plic_reg_pkg::*; #(
// Assertions
`ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
`ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
`ASSERT_KNOWN(AlertKnownO_A, alert_tx_o)
`ASSERT_KNOWN(IrqKnownO_A, irq_o)
`ASSERT_KNOWN(MsipKnownO_A, msip_o)
for (genvar k = 0; k < NumTarget; k++) begin : gen_irq_id_known
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1 change: 1 addition & 0 deletions hw/vendor/lowrisc_ip/ip_templates/rv_plic/rtl/rv_plic.sv.tpl
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Expand Up @@ -273,6 +273,7 @@ module ${module_instance_name} import ${module_instance_name}_reg_pkg::*; #(
% if racl_support:
`ASSERT_KNOWN(RaclErrorValidKnown_A, racl_error_o.valid)
% endif
`ASSERT_KNOWN(AlertKnownO_A, alert_tx_o)
`ASSERT_KNOWN(IrqKnownO_A, irq_o)
`ASSERT_KNOWN(MsipKnownO_A, msip_o)
for (genvar k = 0; k < NumTarget; k++) begin : gen_irq_id_known
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12 changes: 12 additions & 0 deletions hw/vendor/patches/lowrisc_ip/rv_plic/0002_Add_Missing_Output_Assertion.patch
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@@ -0,0 +1,12 @@
diff --git a/rtl/rv_plic.sv.tpl b/rtl/rv_plic.sv.tpl
index 9f2cc636..d8b83094 100644
--- a/rtl/rv_plic.sv.tpl
+++ b/rtl/rv_plic.sv.tpl
@@ -273,6 +273,7 @@ module ${module_instance_name} import ${module_instance_name}_reg_pkg::*; #(
% if racl_support:
`ASSERT_KNOWN(RaclErrorValidKnown_A, racl_error_o.valid)
% endif
+ `ASSERT_KNOWN(AlertKnownO_A, alert_tx_o)
`ASSERT_KNOWN(IrqKnownO_A, irq_o)
`ASSERT_KNOWN(MsipKnownO_A, msip_o)
for (genvar k = 0; k < NumTarget; k++) begin : gen_irq_id_known