[rtl,CHERIoT] Properly track outstanding memory transactions assertions - #2502
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SamuelRiedel wants to merge 2 commits into
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The CHERIoT clc/csc where not properly taken into account in this assertion, leading to false positives. Signed-off-by: Samuel Riedel <sriedel@lowrisc.org>
- Ensure a CHERIoT LSU request is mutually exclusive with other multicycle signals - Ensure the LSU doesn't issue any CHERIoT requests while the ID stage is stalled Signed-off-by: Samuel Riedel <sriedel@lowrisc.org>
gautschimi
reviewed
Sep 14, 2026
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| // lsu_busy covers all non-IDLE states, but in WAIT_GNT the second grant hasn't been issued yet | ||
| // so no outstandng response can arrive there. | ||
| assign lsu_expecting_resp = lsu_busy & (load_store_unit_i.ls_fsm_cs != WAIT_GNT); |
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lsu_expecting_resp is declared/assigned outside if (WritebackStage) but only ever read inside it. WritebackStage defaults to 0, so this looks like it'll be an unused-signal lint warning in that config unless CI only lints WritebackStage=1. Might want to move the declaration/assign inside the if (WritebackStage) block.
| (id_stage_i.lsu_req_dec | id_stage_i.cheriot_lsu_req_dec) & | ||
| id_stage_i.lsu_we; | ||
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| // lsu_busy covers all non-IDLE states, but in WAIT_GNT the second grant hasn't been issued yet |
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Not quite sure I understand this comment
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| // lsu_busy covers all non-IDLE states, but in WAIT_GNT the second grant hasn't been issued yet | ||
| // so no outstandng response can arrive there. | ||
| assign lsu_expecting_resp = lsu_busy & (load_store_unit_i.ls_fsm_cs != WAIT_GNT); |
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also load_store_unit_i.ls_fsm_cs is a hierarchical assignment. please avoid. lets route this condition out of the LSU
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CHERIoT uses its own LSU request signals which were missing from some assertions tracking different LSU properties. This aligns the CHERIoT capability load/stores, which are two memory transactions, with the unaligned load/stores, which do the same. Simultaneously, we also fix a few edgecases, where the NoMemResponseWithoutPendingAccess could give false positives.