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1. openhwgroup/cva6 openhwgroup/cva6 Public

   The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

   Assembly 3.1k 1k

2. pulp-platform/riscv-dbg pulp-platform/riscv-dbg Public

   RISC-V Debug Support for our PULP RISC-V Cores

   SystemVerilog 326 102

3. riscv-ooo-core riscv-ooo-core Public

   Full superscalar RV32I out-of-order processor with Tomasulos Algorithm, 7-stage pipeline, and UVM testbench. 1st Place + Special Jury Award — SanDisk Hardware Hackathon.

   Verilog 13

4. constraintforge constraintforge Public

   Production-grade FPGA timing constraint library for Xilinx UltraScale+. Modular, parametric XDC templates for high-speed digital design.

   Tcl 6 1