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Fearless hardware design
Verilog 209 12
Time-sensitive affine types for predictable hardware generation
Scala 152 11
rules for writing and typesetting
SCSS 26 6
generating hardware accelerators for pangenomic graph queries
Rust 45 3
TeX 9
New implementation of protocols
Rust 15
Math Library Generator for Calyx
a research group site
and-inverter graphs in rust for formal verification / circuit synthesis
BitVector and Array Arithmetic library
DO NOT EDIT. Deployment repository for docs.calyxir.org
work in progress, playing around with btor2 in rust
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