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OpenPOWERFoundation
microwatt
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hello_world: debug print of the gitinfo syscon register
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#215:
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xics: Fix warning when comparing two std_ulogic_vectors
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Orange Crab is 48MHz not 50MHz, bump PLL frequency
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decode1: Fix maddld and maddhdu to not set CR0
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Remove unused sequential signal from Fetch1ToIcacheType
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Xilinx FPGAs: Eliminate Vivado critical warnings
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Run VUnit tests in CI
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loadstore1: Split DAWR check across a clock edge
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core: Allow multiple loadstore instructions to be in flight
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[genesys2] Fix DDR3 PHY cmd_latency
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VUnit: style
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FPU: Update committed FPSCR value correctly
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xics: Rework the irq_gen process
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openocd: Fix verify command for v0.10
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fetch1: Implement a simple branch target cache
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minor fix --removing vhdl 2008 features
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tests: Update metavalues test count
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syscon: Remove combinational loop on ack and stall
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#198:
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Use $(GHDL) rather than ghdl in Makefile
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litedram: L2 use latched refill_index
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dcache: Simplify forwarding of load data while reloading a cache line
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MMU: Implement a vestigial partition table
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arty_a7: Add litesdcard interface
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core: Make popcnt* take two cycles
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multiply_tb: Fix multiply_tb.vhdl for the new multiplier interface
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