From 5b929c38d8333bd6bdec66f94eca61d038e2be18 Mon Sep 17 00:00:00 2001 From: Raphael Roth Date: Thu, 3 Sep 2026 10:55:22 +0200 Subject: [PATCH 1/3] [keymgr_dpe, hjson] Append `metadata` register These registers enable the metadata for each DPE context stored inside the HW slot to be read. For any uninstantiated hw slot the register will return `0` for all entries. Signed-off-by: Raphael Roth --- hw/ip/keymgr_dpe/data/keymgr_dpe.hjson | 93 ++ hw/ip/keymgr_dpe/doc/registers.md | 131 ++- hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv | 8 + hw/ip/keymgr_dpe/rtl/keymgr_dpe_reg_pkg.sv | 278 +++-- hw/ip/keymgr_dpe/rtl/keymgr_dpe_reg_top.sv | 1020 ++++++++++++++++- .../data/autogen/top_darjeeling.gen.hjson | 2 +- hw/top_darjeeling/doc/memory_map.md | 2 +- .../dv/autogen/xbar_env_pkg__params.sv | 2 +- .../dv/autogen/xbar_tgl_excl.cfg | 2 +- .../data/autogen/xbar_main.gen.hjson | 2 +- .../ip/xbar_main/dv/autogen/xbar_cover.cfg | 2 +- .../dv/autogen/xbar_env_pkg__params.sv | 2 +- .../ip/xbar_main/rtl/autogen/tl_main_pkg.sv | 2 +- .../rtl/autogen/top_darjeeling_pkg.sv | 2 +- .../sw/autogen/chip/top_darjeeling.rs | 2 +- hw/top_darjeeling/sw/autogen/top_darjeeling.h | 2 +- hw/top_darjeeling/sw/autogen/top_memory.h | 2 +- .../data/autogen/top_earlgrey.gen.hjson | 2 +- hw/top_earlgrey/doc/memory_map.md | 2 +- .../dv/autogen/xbar_env_pkg__params.sv | 2 +- hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg | 2 +- .../data/autogen/xbar_main.gen.hjson | 2 +- .../ip/xbar_main/dv/autogen/xbar_cover.cfg | 2 +- .../dv/autogen/xbar_env_pkg__params.sv | 2 +- .../ip/xbar_main/rtl/autogen/tl_main_pkg.sv | 2 +- .../rtl/autogen/top_earlgrey_pkg.sv | 2 +- .../sw/autogen/chip/top_earlgrey.rs | 2 +- hw/top_earlgrey/sw/autogen/top_earlgrey.h | 2 +- hw/top_earlgrey/sw/autogen/top_memory.h | 2 +- 29 files changed, 1457 insertions(+), 121 deletions(-) diff --git a/hw/ip/keymgr_dpe/data/keymgr_dpe.hjson b/hw/ip/keymgr_dpe/data/keymgr_dpe.hjson index 703089b13ac0e..4b90eeb337bc9 100644 --- a/hw/ip/keymgr_dpe/data/keymgr_dpe.hjson +++ b/hw/ip/keymgr_dpe/data/keymgr_dpe.hjson @@ -1002,6 +1002,99 @@ countermeasures: [ ] }, + { multireg: { + cname: "KEYMGR", + name: "METADATA_LOW", + desc: ''' + Read metadata (low word) for each HW slot. + + Only the first `NumInstHwSlot` slots are instantiated. + Entries at index `NumInstHwSlot` and above always read as 0. + Together with !!METADATA_HIGH, this register lets software inspect the non-secret + metadata of the DPE context. + ''', + count: "NumMaxHwSlot", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "31:0", + name: "MAX_KEY_VERSION", + desc: ''' + Maximum key version allowed for key derived from this DPE context. + ''', + resval: "0" + }, + ], + }, + }, + + { multireg: { + cname: "KEYMGR", + name: "METADATA_HIGH", + desc: ''' + Read metadata (high word) for each HW slot. + + Only the first `NumInstHwSlot` slots are instantiated. + Entries at index `NumInstHwSlot` and above always read as 0. + Together with !!METADATA_LOW, this register lets software inspect the non-secret + metadata of the DPE context. + ''', + count: "NumMaxHwSlot", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "0", + name: "VALID", + desc: ''' + Set if the DPE context held in this slot is valid. + ''', + resval: "0" + }, + { bits: "2:1", + name: "BOOT_STAGE", + desc: ''' + Boot stage associated with the DPE context held in this slot. + + | Value | Boot stage | + |:-----:|:------------------| + | 0 | BootStageCreator | + | 1 | BootStageOwnerInt | + | 2 | BootStageOwner | + | 3 | BootStageRuntime | + + The naming indicates the next bootstage after a successful key derivation + e.g. boot stage 1 means the context is the _CreatorRootKey_ and will be + derived into the _OwnerIntKey_. + ''', + resval: "0" + }, + { bits: "3", + name: "ALLOW_CHILD_POLICY", + resval: "0" + desc: ''' + Read the `allow_child` policy applied to the DPE context in this slot. + ''' + }, + { bits: "4", + name: "EXPORTABLE_POLICY", + resval: "0" + desc: ''' + Read the `exportable` policy applied to the DPE context in this slot. + ''' + }, + { bits: "5", + name: "RETAIN_PARENT_POLICY", + resval: "0" + desc: ''' + Read the `retain_parent` policy applied to the DPE context in this slot. + ''' + }, + ], + }, + }, + { name: "ERR_CODE", desc: ''' Key manager error code. diff --git a/hw/ip/keymgr_dpe/doc/registers.md b/hw/ip/keymgr_dpe/doc/registers.md index fe83b3486413d..7abc7a631b95d 100644 --- a/hw/ip/keymgr_dpe/doc/registers.md +++ b/hw/ip/keymgr_dpe/doc/registers.md @@ -55,10 +55,26 @@ | keymgr_dpe.[`SW_SHARE1_OUTPUT_7`](#sw_share1_output) | 0xbc | 4 | Key manager software output. | | keymgr_dpe.[`WORKING_STATE`](#working_state) | 0xc0 | 4 | Key manager working state. | | keymgr_dpe.[`OP_STATUS`](#op_status) | 0xc4 | 4 | Key manager status. | -| keymgr_dpe.[`ERR_CODE`](#err_code) | 0xc8 | 4 | Key manager error code. | -| keymgr_dpe.[`FAULT_STATUS`](#fault_status) | 0xcc | 4 | This register represents both synchronous and asynchronous fatal faults. | -| keymgr_dpe.[`DEBUG`](#debug) | 0xd0 | 4 | The register holds some debug information that may be convenient if keymgr | -| keymgr_dpe.[`LOAD_KEY_LOCK`](#load_key_lock) | 0xd4 | 4 | Register write lock for the LOAD_KEY command | +| keymgr_dpe.[`METADATA_LOW_0`](#metadata_low) | 0xc8 | 4 | Read metadata (low word) for each HW slot. | +| keymgr_dpe.[`METADATA_LOW_1`](#metadata_low) | 0xcc | 4 | Read metadata (low word) for each HW slot. | +| keymgr_dpe.[`METADATA_LOW_2`](#metadata_low) | 0xd0 | 4 | Read metadata (low word) for each HW slot. | +| keymgr_dpe.[`METADATA_LOW_3`](#metadata_low) | 0xd4 | 4 | Read metadata (low word) for each HW slot. | +| keymgr_dpe.[`METADATA_LOW_4`](#metadata_low) | 0xd8 | 4 | Read metadata (low word) for each HW slot. | +| keymgr_dpe.[`METADATA_LOW_5`](#metadata_low) | 0xdc | 4 | Read metadata (low word) for each HW slot. | +| keymgr_dpe.[`METADATA_LOW_6`](#metadata_low) | 0xe0 | 4 | Read metadata (low word) for each HW slot. | +| keymgr_dpe.[`METADATA_LOW_7`](#metadata_low) | 0xe4 | 4 | Read metadata (low word) for each HW slot. | +| keymgr_dpe.[`METADATA_HIGH_0`](#metadata_high) | 0xe8 | 4 | Read metadata (high word) for each HW slot. | +| keymgr_dpe.[`METADATA_HIGH_1`](#metadata_high) | 0xec | 4 | Read metadata (high word) for each HW slot. | +| keymgr_dpe.[`METADATA_HIGH_2`](#metadata_high) | 0xf0 | 4 | Read metadata (high word) for each HW slot. | +| keymgr_dpe.[`METADATA_HIGH_3`](#metadata_high) | 0xf4 | 4 | Read metadata (high word) for each HW slot. | +| keymgr_dpe.[`METADATA_HIGH_4`](#metadata_high) | 0xf8 | 4 | Read metadata (high word) for each HW slot. | +| keymgr_dpe.[`METADATA_HIGH_5`](#metadata_high) | 0xfc | 4 | Read metadata (high word) for each HW slot. | +| keymgr_dpe.[`METADATA_HIGH_6`](#metadata_high) | 0x100 | 4 | Read metadata (high word) for each HW slot. | +| keymgr_dpe.[`METADATA_HIGH_7`](#metadata_high) | 0x104 | 4 | Read metadata (high word) for each HW slot. | +| keymgr_dpe.[`ERR_CODE`](#err_code) | 0x108 | 4 | Key manager error code. | +| keymgr_dpe.[`FAULT_STATUS`](#fault_status) | 0x10c | 4 | This register represents both synchronous and asynchronous fatal faults. | +| keymgr_dpe.[`DEBUG`](#debug) | 0x110 | 4 | The register holds some debug information that may be convenient if keymgr | +| keymgr_dpe.[`LOAD_KEY_LOCK`](#load_key_lock) | 0x114 | 4 | Register write lock for the LOAD_KEY command | ## INTR_STATE Interrupt State Register @@ -605,6 +621,105 @@ Operation status. | 0x3 | DONE_ERROR | Operation finished with errors, please see ERR_CODE register. | +## METADATA_LOW +Read metadata (low word) for each HW slot. + +Only the first `NumInstHwSlot` slots are instantiated. +Entries at index `NumInstHwSlot` and above always read as 0. +Together with [`METADATA_HIGH`](#metadata_high), this register lets software inspect the non-secret +metadata of the DPE context. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:---------------|:---------| +| METADATA_LOW_0 | 0xc8 | +| METADATA_LOW_1 | 0xcc | +| METADATA_LOW_2 | 0xd0 | +| METADATA_LOW_3 | 0xd4 | +| METADATA_LOW_4 | 0xd8 | +| METADATA_LOW_5 | 0xdc | +| METADATA_LOW_6 | 0xe0 | +| METADATA_LOW_7 | 0xe4 | + + +### Fields + +```wavejson +{"reg": [{"name": "MAX_KEY_VERSION", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------|:-------------------------------------------------------------------| +| 31:0 | ro | 0x0 | MAX_KEY_VERSION | Maximum key version allowed for key derived from this DPE context. | + +## METADATA_HIGH +Read metadata (high word) for each HW slot. + +Only the first `NumInstHwSlot` slots are instantiated. +Entries at index `NumInstHwSlot` and above always read as 0. +Together with [`METADATA_LOW`](#metadata_low), this register lets software inspect the non-secret +metadata of the DPE context. +- Reset default: `0x0` +- Reset mask: `0x3f` + +### Instances + +| Name | Offset | +|:----------------|:---------| +| METADATA_HIGH_0 | 0xe8 | +| METADATA_HIGH_1 | 0xec | +| METADATA_HIGH_2 | 0xf0 | +| METADATA_HIGH_3 | 0xf4 | +| METADATA_HIGH_4 | 0xf8 | +| METADATA_HIGH_5 | 0xfc | +| METADATA_HIGH_6 | 0x100 | +| METADATA_HIGH_7 | 0x104 | + + +### Fields + +```wavejson +{"reg": [{"name": "VALID", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "BOOT_STAGE", "bits": 2, "attr": ["ro"], "rotate": -90}, {"name": "ALLOW_CHILD_POLICY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "EXPORTABLE_POLICY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RETAIN_PARENT_POLICY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-------------------------------------------------------------| +| 31:6 | | | Reserved | +| 5 | ro | 0x0 | [RETAIN_PARENT_POLICY](#metadata_high--retain_parent_policy) | +| 4 | ro | 0x0 | [EXPORTABLE_POLICY](#metadata_high--exportable_policy) | +| 3 | ro | 0x0 | [ALLOW_CHILD_POLICY](#metadata_high--allow_child_policy) | +| 2:1 | ro | 0x0 | [BOOT_STAGE](#metadata_high--boot_stage) | +| 0 | ro | 0x0 | [VALID](#metadata_high--valid) | + +### METADATA_HIGH . RETAIN_PARENT_POLICY +Read the `retain_parent` policy applied to the DPE context in this slot. + +### METADATA_HIGH . EXPORTABLE_POLICY +Read the `exportable` policy applied to the DPE context in this slot. + +### METADATA_HIGH . ALLOW_CHILD_POLICY +Read the `allow_child` policy applied to the DPE context in this slot. + +### METADATA_HIGH . BOOT_STAGE +Boot stage associated with the DPE context held in this slot. + +| Value | Boot stage | +|:-----:|:------------------| +| 0 | BootStageCreator | +| 1 | BootStageOwnerInt | +| 2 | BootStageOwner | +| 3 | BootStageRuntime | + +The naming indicates the next bootstage after a successful key derivation +e.g. boot stage 1 means the context is the _CreatorRootKey_ and will be +derived into the _OwnerIntKey_. + +### METADATA_HIGH . VALID +Set if the DPE context held in this slot is valid. + ## ERR_CODE Key manager error code. This register must be explicitly cleared by software. @@ -614,7 +729,7 @@ errors. Synchronous errors refer to those that only happen when a keymgr operation is invoked, while asynchronous refers to errors that can happen at any time. -- Offset: `0xc8` +- Offset: `0x108` - Reset default: `0x0` - Reset mask: `0x7` @@ -637,7 +752,7 @@ This register represents both synchronous and asynchronous fatal faults. Synchronous faults refer to those that only happen when a keymgr operation is invoked, while asynchronous refers to faults that can happen at any time. -- Offset: `0xcc` +- Offset: `0x10c` - Reset default: `0x0` - Reset mask: `0x3fff` @@ -668,7 +783,7 @@ invoked, while asynchronous refers to faults that can happen at any time. ## DEBUG The register holds some debug information that may be convenient if keymgr misbehaves. -- Offset: `0xd0` +- Offset: `0x110` - Reset default: `0x0` - Reset mask: `0x1ff` @@ -693,7 +808,7 @@ misbehaves. ## LOAD_KEY_LOCK Register write lock for the LOAD_KEY command -- Offset: `0xd4` +- Offset: `0x114` - Reset default: `0x0` - Reset mask: `0x1` diff --git a/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv b/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv index a8ca24501f0e2..7e5456b957386 100644 --- a/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv +++ b/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv @@ -289,6 +289,14 @@ module keymgr_dpe logic sideload_sel_err; logic key_version_vld; + for (genvar i = 0; i < NumMaxHwSlot; i++) begin : gen_metadata_read_data + assign hw2reg.metadata_high[i].valid.d = '0; + assign hw2reg.metadata_high[i].exportable_policy.d = '0; + assign hw2reg.metadata_high[i].retain_parent_policy.d = '0; + assign hw2reg.metadata_high[i].allow_child_policy.d = '0; + assign hw2reg.metadata_high[i].boot_stage.d = '0; + assign hw2reg.metadata_low[i].d = '0; + end for (genvar i = 0; i < Shares; i++) begin : gen_truncate_data assign kmac_data_truncated[i] = kmac_data[i][KeyWidth-1:0]; diff --git a/hw/ip/keymgr_dpe/rtl/keymgr_dpe_reg_pkg.sv b/hw/ip/keymgr_dpe/rtl/keymgr_dpe_reg_pkg.sv index 0f1e7a1e115b5..4a6f28fb5e228 100644 --- a/hw/ip/keymgr_dpe/rtl/keymgr_dpe_reg_pkg.sv +++ b/hw/ip/keymgr_dpe/rtl/keymgr_dpe_reg_pkg.sv @@ -15,10 +15,10 @@ package keymgr_dpe_reg_pkg; parameter int NumAlerts = 2; // Address widths within the block - parameter int BlockAw = 8; + parameter int BlockAw = 9; // Number of registers for every interface - parameter int NumRegs = 54; + parameter int NumRegs = 70; // Alert indices typedef enum int { @@ -222,6 +222,28 @@ package keymgr_dpe_reg_pkg; logic de; } keymgr_dpe_hw2reg_op_status_reg_t; + typedef struct packed { + logic [31:0] d; + } keymgr_dpe_hw2reg_metadata_low_mreg_t; + + typedef struct packed { + struct packed { + logic d; + } retain_parent_policy; + struct packed { + logic d; + } exportable_policy; + struct packed { + logic d; + } allow_child_policy; + struct packed { + logic [1:0] d; + } boot_stage; + struct packed { + logic d; + } valid; + } keymgr_dpe_hw2reg_metadata_high_mreg_t; + typedef struct packed { struct packed { logic d; @@ -359,76 +381,94 @@ package keymgr_dpe_reg_pkg; // HW -> register type typedef struct packed { - keymgr_dpe_hw2reg_intr_state_reg_t intr_state; // [593:592] - keymgr_dpe_hw2reg_cfg_regwen_reg_t cfg_regwen; // [591:591] - keymgr_dpe_hw2reg_start_reg_t start; // [590:589] - keymgr_dpe_hw2reg_slot_policy_regwen_reg_t slot_policy_regwen; // [588:588] - keymgr_dpe_hw2reg_sw_binding_regwen_reg_t sw_binding_regwen; // [587:587] - keymgr_dpe_hw2reg_max_key_ver_regwen_reg_t max_key_ver_regwen; // [586:586] - keymgr_dpe_hw2reg_sw_share0_output_mreg_t [7:0] sw_share0_output; // [585:322] - keymgr_dpe_hw2reg_sw_share1_output_mreg_t [7:0] sw_share1_output; // [321:58] - keymgr_dpe_hw2reg_working_state_reg_t working_state; // [57:55] - keymgr_dpe_hw2reg_op_status_reg_t op_status; // [54:52] + keymgr_dpe_hw2reg_intr_state_reg_t intr_state; // [897:896] + keymgr_dpe_hw2reg_cfg_regwen_reg_t cfg_regwen; // [895:895] + keymgr_dpe_hw2reg_start_reg_t start; // [894:893] + keymgr_dpe_hw2reg_slot_policy_regwen_reg_t slot_policy_regwen; // [892:892] + keymgr_dpe_hw2reg_sw_binding_regwen_reg_t sw_binding_regwen; // [891:891] + keymgr_dpe_hw2reg_max_key_ver_regwen_reg_t max_key_ver_regwen; // [890:890] + keymgr_dpe_hw2reg_sw_share0_output_mreg_t [7:0] sw_share0_output; // [889:626] + keymgr_dpe_hw2reg_sw_share1_output_mreg_t [7:0] sw_share1_output; // [625:362] + keymgr_dpe_hw2reg_working_state_reg_t working_state; // [361:359] + keymgr_dpe_hw2reg_op_status_reg_t op_status; // [358:356] + keymgr_dpe_hw2reg_metadata_low_mreg_t [7:0] metadata_low; // [355:100] + keymgr_dpe_hw2reg_metadata_high_mreg_t [7:0] metadata_high; // [99:52] keymgr_dpe_hw2reg_err_code_reg_t err_code; // [51:46] keymgr_dpe_hw2reg_fault_status_reg_t fault_status; // [45:18] keymgr_dpe_hw2reg_debug_reg_t debug; // [17:0] } keymgr_dpe_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] KEYMGR_DPE_INTR_STATE_OFFSET = 8'h 0; - parameter logic [BlockAw-1:0] KEYMGR_DPE_INTR_ENABLE_OFFSET = 8'h 4; - parameter logic [BlockAw-1:0] KEYMGR_DPE_INTR_TEST_OFFSET = 8'h 8; - parameter logic [BlockAw-1:0] KEYMGR_DPE_ALERT_TEST_OFFSET = 8'h c; - parameter logic [BlockAw-1:0] KEYMGR_DPE_CFG_REGWEN_OFFSET = 8'h 10; - parameter logic [BlockAw-1:0] KEYMGR_DPE_START_OFFSET = 8'h 14; - parameter logic [BlockAw-1:0] KEYMGR_DPE_CONTROL_SHADOWED_OFFSET = 8'h 18; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SIDELOAD_CLEAR_OFFSET = 8'h 1c; - parameter logic [BlockAw-1:0] KEYMGR_DPE_RESEED_INTERVAL_REGWEN_OFFSET = 8'h 20; - parameter logic [BlockAw-1:0] KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_OFFSET = 8'h 24; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SLOT_POLICY_REGWEN_OFFSET = 8'h 28; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SLOT_POLICY_OFFSET = 8'h 2c; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_REGWEN_OFFSET = 8'h 30; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_0_OFFSET = 8'h 34; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_1_OFFSET = 8'h 38; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_2_OFFSET = 8'h 3c; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_3_OFFSET = 8'h 40; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_4_OFFSET = 8'h 44; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_5_OFFSET = 8'h 48; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_6_OFFSET = 8'h 4c; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_7_OFFSET = 8'h 50; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_0_OFFSET = 8'h 54; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_1_OFFSET = 8'h 58; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_2_OFFSET = 8'h 5c; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_3_OFFSET = 8'h 60; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_4_OFFSET = 8'h 64; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_5_OFFSET = 8'h 68; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_6_OFFSET = 8'h 6c; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_7_OFFSET = 8'h 70; - parameter logic [BlockAw-1:0] KEYMGR_DPE_KEY_VERSION_OFFSET = 8'h 74; - parameter logic [BlockAw-1:0] KEYMGR_DPE_MAX_KEY_VER_REGWEN_OFFSET = 8'h 78; - parameter logic [BlockAw-1:0] KEYMGR_DPE_MAX_KEY_VER_SHADOWED_OFFSET = 8'h 7c; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_0_OFFSET = 8'h 80; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_1_OFFSET = 8'h 84; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_2_OFFSET = 8'h 88; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_3_OFFSET = 8'h 8c; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_4_OFFSET = 8'h 90; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_5_OFFSET = 8'h 94; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_6_OFFSET = 8'h 98; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_7_OFFSET = 8'h 9c; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_0_OFFSET = 8'h a0; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_1_OFFSET = 8'h a4; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_2_OFFSET = 8'h a8; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_3_OFFSET = 8'h ac; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_4_OFFSET = 8'h b0; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_5_OFFSET = 8'h b4; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_6_OFFSET = 8'h b8; - parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_7_OFFSET = 8'h bc; - parameter logic [BlockAw-1:0] KEYMGR_DPE_WORKING_STATE_OFFSET = 8'h c0; - parameter logic [BlockAw-1:0] KEYMGR_DPE_OP_STATUS_OFFSET = 8'h c4; - parameter logic [BlockAw-1:0] KEYMGR_DPE_ERR_CODE_OFFSET = 8'h c8; - parameter logic [BlockAw-1:0] KEYMGR_DPE_FAULT_STATUS_OFFSET = 8'h cc; - parameter logic [BlockAw-1:0] KEYMGR_DPE_DEBUG_OFFSET = 8'h d0; - parameter logic [BlockAw-1:0] KEYMGR_DPE_LOAD_KEY_LOCK_OFFSET = 8'h d4; + parameter logic [BlockAw-1:0] KEYMGR_DPE_INTR_STATE_OFFSET = 9'h 0; + parameter logic [BlockAw-1:0] KEYMGR_DPE_INTR_ENABLE_OFFSET = 9'h 4; + parameter logic [BlockAw-1:0] KEYMGR_DPE_INTR_TEST_OFFSET = 9'h 8; + parameter logic [BlockAw-1:0] KEYMGR_DPE_ALERT_TEST_OFFSET = 9'h c; + parameter logic [BlockAw-1:0] KEYMGR_DPE_CFG_REGWEN_OFFSET = 9'h 10; + parameter logic [BlockAw-1:0] KEYMGR_DPE_START_OFFSET = 9'h 14; + parameter logic [BlockAw-1:0] KEYMGR_DPE_CONTROL_SHADOWED_OFFSET = 9'h 18; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SIDELOAD_CLEAR_OFFSET = 9'h 1c; + parameter logic [BlockAw-1:0] KEYMGR_DPE_RESEED_INTERVAL_REGWEN_OFFSET = 9'h 20; + parameter logic [BlockAw-1:0] KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_OFFSET = 9'h 24; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SLOT_POLICY_REGWEN_OFFSET = 9'h 28; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SLOT_POLICY_OFFSET = 9'h 2c; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_REGWEN_OFFSET = 9'h 30; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_0_OFFSET = 9'h 34; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_1_OFFSET = 9'h 38; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_2_OFFSET = 9'h 3c; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_3_OFFSET = 9'h 40; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_4_OFFSET = 9'h 44; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_5_OFFSET = 9'h 48; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_6_OFFSET = 9'h 4c; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_BINDING_7_OFFSET = 9'h 50; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_0_OFFSET = 9'h 54; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_1_OFFSET = 9'h 58; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_2_OFFSET = 9'h 5c; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_3_OFFSET = 9'h 60; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_4_OFFSET = 9'h 64; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_5_OFFSET = 9'h 68; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_6_OFFSET = 9'h 6c; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SALT_7_OFFSET = 9'h 70; + parameter logic [BlockAw-1:0] KEYMGR_DPE_KEY_VERSION_OFFSET = 9'h 74; + parameter logic [BlockAw-1:0] KEYMGR_DPE_MAX_KEY_VER_REGWEN_OFFSET = 9'h 78; + parameter logic [BlockAw-1:0] KEYMGR_DPE_MAX_KEY_VER_SHADOWED_OFFSET = 9'h 7c; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_0_OFFSET = 9'h 80; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_1_OFFSET = 9'h 84; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_2_OFFSET = 9'h 88; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_3_OFFSET = 9'h 8c; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_4_OFFSET = 9'h 90; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_5_OFFSET = 9'h 94; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_6_OFFSET = 9'h 98; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE0_OUTPUT_7_OFFSET = 9'h 9c; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_0_OFFSET = 9'h a0; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_1_OFFSET = 9'h a4; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_2_OFFSET = 9'h a8; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_3_OFFSET = 9'h ac; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_4_OFFSET = 9'h b0; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_5_OFFSET = 9'h b4; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_6_OFFSET = 9'h b8; + parameter logic [BlockAw-1:0] KEYMGR_DPE_SW_SHARE1_OUTPUT_7_OFFSET = 9'h bc; + parameter logic [BlockAw-1:0] KEYMGR_DPE_WORKING_STATE_OFFSET = 9'h c0; + parameter logic [BlockAw-1:0] KEYMGR_DPE_OP_STATUS_OFFSET = 9'h c4; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_LOW_0_OFFSET = 9'h c8; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_LOW_1_OFFSET = 9'h cc; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_LOW_2_OFFSET = 9'h d0; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_LOW_3_OFFSET = 9'h d4; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_LOW_4_OFFSET = 9'h d8; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_LOW_5_OFFSET = 9'h dc; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_LOW_6_OFFSET = 9'h e0; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_LOW_7_OFFSET = 9'h e4; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_HIGH_0_OFFSET = 9'h e8; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_HIGH_1_OFFSET = 9'h ec; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_HIGH_2_OFFSET = 9'h f0; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_HIGH_3_OFFSET = 9'h f4; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_HIGH_4_OFFSET = 9'h f8; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_HIGH_5_OFFSET = 9'h fc; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_HIGH_6_OFFSET = 9'h 100; + parameter logic [BlockAw-1:0] KEYMGR_DPE_METADATA_HIGH_7_OFFSET = 9'h 104; + parameter logic [BlockAw-1:0] KEYMGR_DPE_ERR_CODE_OFFSET = 9'h 108; + parameter logic [BlockAw-1:0] KEYMGR_DPE_FAULT_STATUS_OFFSET = 9'h 10c; + parameter logic [BlockAw-1:0] KEYMGR_DPE_DEBUG_OFFSET = 9'h 110; + parameter logic [BlockAw-1:0] KEYMGR_DPE_LOAD_KEY_LOCK_OFFSET = 9'h 114; // Reset values for hwext registers and their fields parameter logic [0:0] KEYMGR_DPE_INTR_TEST_RESVAL = 1'h 0; @@ -444,6 +484,70 @@ package keymgr_dpe_reg_pkg; parameter logic [0:0] KEYMGR_DPE_SW_BINDING_REGWEN_EN_RESVAL = 1'h 1; parameter logic [0:0] KEYMGR_DPE_MAX_KEY_VER_REGWEN_RESVAL = 1'h 1; parameter logic [0:0] KEYMGR_DPE_MAX_KEY_VER_REGWEN_EN_RESVAL = 1'h 1; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_0_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_0_MAX_KEY_VERSION_0_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_1_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_1_MAX_KEY_VERSION_1_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_2_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_2_MAX_KEY_VERSION_2_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_3_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_3_MAX_KEY_VERSION_3_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_4_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_4_MAX_KEY_VERSION_4_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_5_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_5_MAX_KEY_VERSION_5_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_6_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_6_MAX_KEY_VERSION_6_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_7_RESVAL = 32'h 0; + parameter logic [31:0] KEYMGR_DPE_METADATA_LOW_7_MAX_KEY_VERSION_7_RESVAL = 32'h 0; + parameter logic [5:0] KEYMGR_DPE_METADATA_HIGH_0_RESVAL = 6'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_0_VALID_0_RESVAL = 1'h 0; + parameter logic [1:0] KEYMGR_DPE_METADATA_HIGH_0_BOOT_STAGE_0_RESVAL = 2'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_0_ALLOW_CHILD_POLICY_0_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_0_EXPORTABLE_POLICY_0_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_0_RETAIN_PARENT_POLICY_0_RESVAL = 1'h 0; + parameter logic [5:0] KEYMGR_DPE_METADATA_HIGH_1_RESVAL = 6'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_1_VALID_1_RESVAL = 1'h 0; + parameter logic [1:0] KEYMGR_DPE_METADATA_HIGH_1_BOOT_STAGE_1_RESVAL = 2'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_1_ALLOW_CHILD_POLICY_1_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_1_EXPORTABLE_POLICY_1_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_1_RETAIN_PARENT_POLICY_1_RESVAL = 1'h 0; + parameter logic [5:0] KEYMGR_DPE_METADATA_HIGH_2_RESVAL = 6'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_2_VALID_2_RESVAL = 1'h 0; + parameter logic [1:0] KEYMGR_DPE_METADATA_HIGH_2_BOOT_STAGE_2_RESVAL = 2'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_2_ALLOW_CHILD_POLICY_2_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_2_EXPORTABLE_POLICY_2_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_2_RETAIN_PARENT_POLICY_2_RESVAL = 1'h 0; + parameter logic [5:0] KEYMGR_DPE_METADATA_HIGH_3_RESVAL = 6'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_3_VALID_3_RESVAL = 1'h 0; + parameter logic [1:0] KEYMGR_DPE_METADATA_HIGH_3_BOOT_STAGE_3_RESVAL = 2'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_3_ALLOW_CHILD_POLICY_3_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_3_EXPORTABLE_POLICY_3_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_3_RETAIN_PARENT_POLICY_3_RESVAL = 1'h 0; + parameter logic [5:0] KEYMGR_DPE_METADATA_HIGH_4_RESVAL = 6'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_4_VALID_4_RESVAL = 1'h 0; + parameter logic [1:0] KEYMGR_DPE_METADATA_HIGH_4_BOOT_STAGE_4_RESVAL = 2'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_4_ALLOW_CHILD_POLICY_4_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_4_EXPORTABLE_POLICY_4_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_4_RETAIN_PARENT_POLICY_4_RESVAL = 1'h 0; + parameter logic [5:0] KEYMGR_DPE_METADATA_HIGH_5_RESVAL = 6'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_5_VALID_5_RESVAL = 1'h 0; + parameter logic [1:0] KEYMGR_DPE_METADATA_HIGH_5_BOOT_STAGE_5_RESVAL = 2'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_5_ALLOW_CHILD_POLICY_5_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_5_EXPORTABLE_POLICY_5_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_5_RETAIN_PARENT_POLICY_5_RESVAL = 1'h 0; + parameter logic [5:0] KEYMGR_DPE_METADATA_HIGH_6_RESVAL = 6'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_6_VALID_6_RESVAL = 1'h 0; + parameter logic [1:0] KEYMGR_DPE_METADATA_HIGH_6_BOOT_STAGE_6_RESVAL = 2'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_6_ALLOW_CHILD_POLICY_6_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_6_EXPORTABLE_POLICY_6_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_6_RETAIN_PARENT_POLICY_6_RESVAL = 1'h 0; + parameter logic [5:0] KEYMGR_DPE_METADATA_HIGH_7_RESVAL = 6'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_7_VALID_7_RESVAL = 1'h 0; + parameter logic [1:0] KEYMGR_DPE_METADATA_HIGH_7_BOOT_STAGE_7_RESVAL = 2'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_7_ALLOW_CHILD_POLICY_7_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_7_EXPORTABLE_POLICY_7_RESVAL = 1'h 0; + parameter logic [0:0] KEYMGR_DPE_METADATA_HIGH_7_RETAIN_PARENT_POLICY_7_RESVAL = 1'h 0; // Register index typedef enum int { @@ -497,6 +601,22 @@ package keymgr_dpe_reg_pkg; KEYMGR_DPE_SW_SHARE1_OUTPUT_7, KEYMGR_DPE_WORKING_STATE, KEYMGR_DPE_OP_STATUS, + KEYMGR_DPE_METADATA_LOW_0, + KEYMGR_DPE_METADATA_LOW_1, + KEYMGR_DPE_METADATA_LOW_2, + KEYMGR_DPE_METADATA_LOW_3, + KEYMGR_DPE_METADATA_LOW_4, + KEYMGR_DPE_METADATA_LOW_5, + KEYMGR_DPE_METADATA_LOW_6, + KEYMGR_DPE_METADATA_LOW_7, + KEYMGR_DPE_METADATA_HIGH_0, + KEYMGR_DPE_METADATA_HIGH_1, + KEYMGR_DPE_METADATA_HIGH_2, + KEYMGR_DPE_METADATA_HIGH_3, + KEYMGR_DPE_METADATA_HIGH_4, + KEYMGR_DPE_METADATA_HIGH_5, + KEYMGR_DPE_METADATA_HIGH_6, + KEYMGR_DPE_METADATA_HIGH_7, KEYMGR_DPE_ERR_CODE, KEYMGR_DPE_FAULT_STATUS, KEYMGR_DPE_DEBUG, @@ -504,7 +624,7 @@ package keymgr_dpe_reg_pkg; } keymgr_dpe_id_e; // Register width information to check illegal writes - parameter logic [3:0] KEYMGR_DPE_PERMIT [54] = '{ + parameter logic [3:0] KEYMGR_DPE_PERMIT [70] = '{ 4'b 0001, // index[ 0] KEYMGR_DPE_INTR_STATE 4'b 0001, // index[ 1] KEYMGR_DPE_INTR_ENABLE 4'b 0001, // index[ 2] KEYMGR_DPE_INTR_TEST @@ -555,10 +675,26 @@ package keymgr_dpe_reg_pkg; 4'b 1111, // index[47] KEYMGR_DPE_SW_SHARE1_OUTPUT_7 4'b 0001, // index[48] KEYMGR_DPE_WORKING_STATE 4'b 0001, // index[49] KEYMGR_DPE_OP_STATUS - 4'b 0001, // index[50] KEYMGR_DPE_ERR_CODE - 4'b 0011, // index[51] KEYMGR_DPE_FAULT_STATUS - 4'b 0011, // index[52] KEYMGR_DPE_DEBUG - 4'b 0001 // index[53] KEYMGR_DPE_LOAD_KEY_LOCK + 4'b 1111, // index[50] KEYMGR_DPE_METADATA_LOW_0 + 4'b 1111, // index[51] KEYMGR_DPE_METADATA_LOW_1 + 4'b 1111, // index[52] KEYMGR_DPE_METADATA_LOW_2 + 4'b 1111, // index[53] KEYMGR_DPE_METADATA_LOW_3 + 4'b 1111, // index[54] KEYMGR_DPE_METADATA_LOW_4 + 4'b 1111, // index[55] KEYMGR_DPE_METADATA_LOW_5 + 4'b 1111, // index[56] KEYMGR_DPE_METADATA_LOW_6 + 4'b 1111, // index[57] KEYMGR_DPE_METADATA_LOW_7 + 4'b 0001, // index[58] KEYMGR_DPE_METADATA_HIGH_0 + 4'b 0001, // index[59] KEYMGR_DPE_METADATA_HIGH_1 + 4'b 0001, // index[60] KEYMGR_DPE_METADATA_HIGH_2 + 4'b 0001, // index[61] KEYMGR_DPE_METADATA_HIGH_3 + 4'b 0001, // index[62] KEYMGR_DPE_METADATA_HIGH_4 + 4'b 0001, // index[63] KEYMGR_DPE_METADATA_HIGH_5 + 4'b 0001, // index[64] KEYMGR_DPE_METADATA_HIGH_6 + 4'b 0001, // index[65] KEYMGR_DPE_METADATA_HIGH_7 + 4'b 0001, // index[66] KEYMGR_DPE_ERR_CODE + 4'b 0011, // index[67] KEYMGR_DPE_FAULT_STATUS + 4'b 0011, // index[68] KEYMGR_DPE_DEBUG + 4'b 0001 // index[69] KEYMGR_DPE_LOAD_KEY_LOCK }; endpackage diff --git a/hw/ip/keymgr_dpe/rtl/keymgr_dpe_reg_top.sv b/hw/ip/keymgr_dpe/rtl/keymgr_dpe_reg_top.sv index b19193b99b187..ee75440db119a 100644 --- a/hw/ip/keymgr_dpe/rtl/keymgr_dpe_reg_top.sv +++ b/hw/ip/keymgr_dpe/rtl/keymgr_dpe_reg_top.sv @@ -25,7 +25,7 @@ module keymgr_dpe_reg_top ( import keymgr_dpe_reg_pkg::* ; - localparam int AW = 8; + localparam int AW = 9; localparam int DW = 32; localparam int DBW = DW/8; // Byte Width @@ -56,9 +56,9 @@ module keymgr_dpe_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [53:0] reg_we_check; + logic [69:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(54) + .OneHotWidth(70) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -303,6 +303,70 @@ module keymgr_dpe_reg_top ( logic op_status_we; logic [1:0] op_status_qs; logic [1:0] op_status_wd; + logic metadata_low_0_re; + logic [31:0] metadata_low_0_qs; + logic metadata_low_1_re; + logic [31:0] metadata_low_1_qs; + logic metadata_low_2_re; + logic [31:0] metadata_low_2_qs; + logic metadata_low_3_re; + logic [31:0] metadata_low_3_qs; + logic metadata_low_4_re; + logic [31:0] metadata_low_4_qs; + logic metadata_low_5_re; + logic [31:0] metadata_low_5_qs; + logic metadata_low_6_re; + logic [31:0] metadata_low_6_qs; + logic metadata_low_7_re; + logic [31:0] metadata_low_7_qs; + logic metadata_high_0_re; + logic metadata_high_0_valid_0_qs; + logic [1:0] metadata_high_0_boot_stage_0_qs; + logic metadata_high_0_allow_child_policy_0_qs; + logic metadata_high_0_exportable_policy_0_qs; + logic metadata_high_0_retain_parent_policy_0_qs; + logic metadata_high_1_re; + logic metadata_high_1_valid_1_qs; + logic [1:0] metadata_high_1_boot_stage_1_qs; + logic metadata_high_1_allow_child_policy_1_qs; + logic metadata_high_1_exportable_policy_1_qs; + logic metadata_high_1_retain_parent_policy_1_qs; + logic metadata_high_2_re; + logic metadata_high_2_valid_2_qs; + logic [1:0] metadata_high_2_boot_stage_2_qs; + logic metadata_high_2_allow_child_policy_2_qs; + logic metadata_high_2_exportable_policy_2_qs; + logic metadata_high_2_retain_parent_policy_2_qs; + logic metadata_high_3_re; + logic metadata_high_3_valid_3_qs; + logic [1:0] metadata_high_3_boot_stage_3_qs; + logic metadata_high_3_allow_child_policy_3_qs; + logic metadata_high_3_exportable_policy_3_qs; + logic metadata_high_3_retain_parent_policy_3_qs; + logic metadata_high_4_re; + logic metadata_high_4_valid_4_qs; + logic [1:0] metadata_high_4_boot_stage_4_qs; + logic metadata_high_4_allow_child_policy_4_qs; + logic metadata_high_4_exportable_policy_4_qs; + logic metadata_high_4_retain_parent_policy_4_qs; + logic metadata_high_5_re; + logic metadata_high_5_valid_5_qs; + logic [1:0] metadata_high_5_boot_stage_5_qs; + logic metadata_high_5_allow_child_policy_5_qs; + logic metadata_high_5_exportable_policy_5_qs; + logic metadata_high_5_retain_parent_policy_5_qs; + logic metadata_high_6_re; + logic metadata_high_6_valid_6_qs; + logic [1:0] metadata_high_6_boot_stage_6_qs; + logic metadata_high_6_allow_child_policy_6_qs; + logic metadata_high_6_exportable_policy_6_qs; + logic metadata_high_6_retain_parent_policy_6_qs; + logic metadata_high_7_re; + logic metadata_high_7_valid_7_qs; + logic [1:0] metadata_high_7_boot_stage_7_qs; + logic metadata_high_7_allow_child_policy_7_qs; + logic metadata_high_7_exportable_policy_7_qs; + logic metadata_high_7_retain_parent_policy_7_qs; logic err_code_we; logic err_code_invalid_op_qs; logic err_code_invalid_op_wd; @@ -2043,6 +2107,766 @@ module keymgr_dpe_reg_top ( ); + // Subregister 0 of Multireg metadata_low + // R[metadata_low_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_metadata_low_0 ( + .re (metadata_low_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_low[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_low_0_qs) + ); + + + // Subregister 1 of Multireg metadata_low + // R[metadata_low_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_metadata_low_1 ( + .re (metadata_low_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_low[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_low_1_qs) + ); + + + // Subregister 2 of Multireg metadata_low + // R[metadata_low_2]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_metadata_low_2 ( + .re (metadata_low_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_low[2].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_low_2_qs) + ); + + + // Subregister 3 of Multireg metadata_low + // R[metadata_low_3]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_metadata_low_3 ( + .re (metadata_low_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_low[3].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_low_3_qs) + ); + + + // Subregister 4 of Multireg metadata_low + // R[metadata_low_4]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_metadata_low_4 ( + .re (metadata_low_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_low[4].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_low_4_qs) + ); + + + // Subregister 5 of Multireg metadata_low + // R[metadata_low_5]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_metadata_low_5 ( + .re (metadata_low_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_low[5].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_low_5_qs) + ); + + + // Subregister 6 of Multireg metadata_low + // R[metadata_low_6]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_metadata_low_6 ( + .re (metadata_low_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_low[6].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_low_6_qs) + ); + + + // Subregister 7 of Multireg metadata_low + // R[metadata_low_7]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_metadata_low_7 ( + .re (metadata_low_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_low[7].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_low_7_qs) + ); + + + // Subregister 0 of Multireg metadata_high + // R[metadata_high_0]: V(True) + // F[valid_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_0_valid_0 ( + .re (metadata_high_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[0].valid.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_0_valid_0_qs) + ); + + // F[boot_stage_0]: 2:1 + prim_subreg_ext #( + .DW (2) + ) u_metadata_high_0_boot_stage_0 ( + .re (metadata_high_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[0].boot_stage.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_0_boot_stage_0_qs) + ); + + // F[allow_child_policy_0]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_0_allow_child_policy_0 ( + .re (metadata_high_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[0].allow_child_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_0_allow_child_policy_0_qs) + ); + + // F[exportable_policy_0]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_0_exportable_policy_0 ( + .re (metadata_high_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[0].exportable_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_0_exportable_policy_0_qs) + ); + + // F[retain_parent_policy_0]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_0_retain_parent_policy_0 ( + .re (metadata_high_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[0].retain_parent_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_0_retain_parent_policy_0_qs) + ); + + + // Subregister 1 of Multireg metadata_high + // R[metadata_high_1]: V(True) + // F[valid_1]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_1_valid_1 ( + .re (metadata_high_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[1].valid.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_1_valid_1_qs) + ); + + // F[boot_stage_1]: 2:1 + prim_subreg_ext #( + .DW (2) + ) u_metadata_high_1_boot_stage_1 ( + .re (metadata_high_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[1].boot_stage.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_1_boot_stage_1_qs) + ); + + // F[allow_child_policy_1]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_1_allow_child_policy_1 ( + .re (metadata_high_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[1].allow_child_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_1_allow_child_policy_1_qs) + ); + + // F[exportable_policy_1]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_1_exportable_policy_1 ( + .re (metadata_high_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[1].exportable_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_1_exportable_policy_1_qs) + ); + + // F[retain_parent_policy_1]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_1_retain_parent_policy_1 ( + .re (metadata_high_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[1].retain_parent_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_1_retain_parent_policy_1_qs) + ); + + + // Subregister 2 of Multireg metadata_high + // R[metadata_high_2]: V(True) + // F[valid_2]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_2_valid_2 ( + .re (metadata_high_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[2].valid.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_2_valid_2_qs) + ); + + // F[boot_stage_2]: 2:1 + prim_subreg_ext #( + .DW (2) + ) u_metadata_high_2_boot_stage_2 ( + .re (metadata_high_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[2].boot_stage.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_2_boot_stage_2_qs) + ); + + // F[allow_child_policy_2]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_2_allow_child_policy_2 ( + .re (metadata_high_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[2].allow_child_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_2_allow_child_policy_2_qs) + ); + + // F[exportable_policy_2]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_2_exportable_policy_2 ( + .re (metadata_high_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[2].exportable_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_2_exportable_policy_2_qs) + ); + + // F[retain_parent_policy_2]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_2_retain_parent_policy_2 ( + .re (metadata_high_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[2].retain_parent_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_2_retain_parent_policy_2_qs) + ); + + + // Subregister 3 of Multireg metadata_high + // R[metadata_high_3]: V(True) + // F[valid_3]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_3_valid_3 ( + .re (metadata_high_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[3].valid.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_3_valid_3_qs) + ); + + // F[boot_stage_3]: 2:1 + prim_subreg_ext #( + .DW (2) + ) u_metadata_high_3_boot_stage_3 ( + .re (metadata_high_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[3].boot_stage.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_3_boot_stage_3_qs) + ); + + // F[allow_child_policy_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_3_allow_child_policy_3 ( + .re (metadata_high_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[3].allow_child_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_3_allow_child_policy_3_qs) + ); + + // F[exportable_policy_3]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_3_exportable_policy_3 ( + .re (metadata_high_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[3].exportable_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_3_exportable_policy_3_qs) + ); + + // F[retain_parent_policy_3]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_3_retain_parent_policy_3 ( + .re (metadata_high_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[3].retain_parent_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_3_retain_parent_policy_3_qs) + ); + + + // Subregister 4 of Multireg metadata_high + // R[metadata_high_4]: V(True) + // F[valid_4]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_4_valid_4 ( + .re (metadata_high_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[4].valid.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_4_valid_4_qs) + ); + + // F[boot_stage_4]: 2:1 + prim_subreg_ext #( + .DW (2) + ) u_metadata_high_4_boot_stage_4 ( + .re (metadata_high_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[4].boot_stage.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_4_boot_stage_4_qs) + ); + + // F[allow_child_policy_4]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_4_allow_child_policy_4 ( + .re (metadata_high_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[4].allow_child_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_4_allow_child_policy_4_qs) + ); + + // F[exportable_policy_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_4_exportable_policy_4 ( + .re (metadata_high_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[4].exportable_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_4_exportable_policy_4_qs) + ); + + // F[retain_parent_policy_4]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_4_retain_parent_policy_4 ( + .re (metadata_high_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[4].retain_parent_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_4_retain_parent_policy_4_qs) + ); + + + // Subregister 5 of Multireg metadata_high + // R[metadata_high_5]: V(True) + // F[valid_5]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_5_valid_5 ( + .re (metadata_high_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[5].valid.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_5_valid_5_qs) + ); + + // F[boot_stage_5]: 2:1 + prim_subreg_ext #( + .DW (2) + ) u_metadata_high_5_boot_stage_5 ( + .re (metadata_high_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[5].boot_stage.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_5_boot_stage_5_qs) + ); + + // F[allow_child_policy_5]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_5_allow_child_policy_5 ( + .re (metadata_high_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[5].allow_child_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_5_allow_child_policy_5_qs) + ); + + // F[exportable_policy_5]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_5_exportable_policy_5 ( + .re (metadata_high_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[5].exportable_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_5_exportable_policy_5_qs) + ); + + // F[retain_parent_policy_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_5_retain_parent_policy_5 ( + .re (metadata_high_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[5].retain_parent_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_5_retain_parent_policy_5_qs) + ); + + + // Subregister 6 of Multireg metadata_high + // R[metadata_high_6]: V(True) + // F[valid_6]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_6_valid_6 ( + .re (metadata_high_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[6].valid.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_6_valid_6_qs) + ); + + // F[boot_stage_6]: 2:1 + prim_subreg_ext #( + .DW (2) + ) u_metadata_high_6_boot_stage_6 ( + .re (metadata_high_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[6].boot_stage.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_6_boot_stage_6_qs) + ); + + // F[allow_child_policy_6]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_6_allow_child_policy_6 ( + .re (metadata_high_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[6].allow_child_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_6_allow_child_policy_6_qs) + ); + + // F[exportable_policy_6]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_6_exportable_policy_6 ( + .re (metadata_high_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[6].exportable_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_6_exportable_policy_6_qs) + ); + + // F[retain_parent_policy_6]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_6_retain_parent_policy_6 ( + .re (metadata_high_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[6].retain_parent_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_6_retain_parent_policy_6_qs) + ); + + + // Subregister 7 of Multireg metadata_high + // R[metadata_high_7]: V(True) + // F[valid_7]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_7_valid_7 ( + .re (metadata_high_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[7].valid.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_7_valid_7_qs) + ); + + // F[boot_stage_7]: 2:1 + prim_subreg_ext #( + .DW (2) + ) u_metadata_high_7_boot_stage_7 ( + .re (metadata_high_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[7].boot_stage.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_7_boot_stage_7_qs) + ); + + // F[allow_child_policy_7]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_7_allow_child_policy_7 ( + .re (metadata_high_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[7].allow_child_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_7_allow_child_policy_7_qs) + ); + + // F[exportable_policy_7]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_7_exportable_policy_7 ( + .re (metadata_high_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[7].exportable_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_7_exportable_policy_7_qs) + ); + + // F[retain_parent_policy_7]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_metadata_high_7_retain_parent_policy_7 ( + .re (metadata_high_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.metadata_high[7].retain_parent_policy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (metadata_high_7_retain_parent_policy_7_qs) + ); + + // R[err_code]: V(False) // F[invalid_op]: 0:0 prim_subreg #( @@ -2780,7 +3604,7 @@ module keymgr_dpe_reg_top ( - logic [53:0] addr_hit; + logic [69:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == KEYMGR_DPE_INTR_STATE_OFFSET); addr_hit[ 1] = (reg_addr == KEYMGR_DPE_INTR_ENABLE_OFFSET); @@ -2832,10 +3656,26 @@ module keymgr_dpe_reg_top ( addr_hit[47] = (reg_addr == KEYMGR_DPE_SW_SHARE1_OUTPUT_7_OFFSET); addr_hit[48] = (reg_addr == KEYMGR_DPE_WORKING_STATE_OFFSET); addr_hit[49] = (reg_addr == KEYMGR_DPE_OP_STATUS_OFFSET); - addr_hit[50] = (reg_addr == KEYMGR_DPE_ERR_CODE_OFFSET); - addr_hit[51] = (reg_addr == KEYMGR_DPE_FAULT_STATUS_OFFSET); - addr_hit[52] = (reg_addr == KEYMGR_DPE_DEBUG_OFFSET); - addr_hit[53] = (reg_addr == KEYMGR_DPE_LOAD_KEY_LOCK_OFFSET); + addr_hit[50] = (reg_addr == KEYMGR_DPE_METADATA_LOW_0_OFFSET); + addr_hit[51] = (reg_addr == KEYMGR_DPE_METADATA_LOW_1_OFFSET); + addr_hit[52] = (reg_addr == KEYMGR_DPE_METADATA_LOW_2_OFFSET); + addr_hit[53] = (reg_addr == KEYMGR_DPE_METADATA_LOW_3_OFFSET); + addr_hit[54] = (reg_addr == KEYMGR_DPE_METADATA_LOW_4_OFFSET); + addr_hit[55] = (reg_addr == KEYMGR_DPE_METADATA_LOW_5_OFFSET); + addr_hit[56] = (reg_addr == KEYMGR_DPE_METADATA_LOW_6_OFFSET); + addr_hit[57] = (reg_addr == KEYMGR_DPE_METADATA_LOW_7_OFFSET); + addr_hit[58] = (reg_addr == KEYMGR_DPE_METADATA_HIGH_0_OFFSET); + addr_hit[59] = (reg_addr == KEYMGR_DPE_METADATA_HIGH_1_OFFSET); + addr_hit[60] = (reg_addr == KEYMGR_DPE_METADATA_HIGH_2_OFFSET); + addr_hit[61] = (reg_addr == KEYMGR_DPE_METADATA_HIGH_3_OFFSET); + addr_hit[62] = (reg_addr == KEYMGR_DPE_METADATA_HIGH_4_OFFSET); + addr_hit[63] = (reg_addr == KEYMGR_DPE_METADATA_HIGH_5_OFFSET); + addr_hit[64] = (reg_addr == KEYMGR_DPE_METADATA_HIGH_6_OFFSET); + addr_hit[65] = (reg_addr == KEYMGR_DPE_METADATA_HIGH_7_OFFSET); + addr_hit[66] = (reg_addr == KEYMGR_DPE_ERR_CODE_OFFSET); + addr_hit[67] = (reg_addr == KEYMGR_DPE_FAULT_STATUS_OFFSET); + addr_hit[68] = (reg_addr == KEYMGR_DPE_DEBUG_OFFSET); + addr_hit[69] = (reg_addr == KEYMGR_DPE_LOAD_KEY_LOCK_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -2896,7 +3736,23 @@ module keymgr_dpe_reg_top ( (addr_hit[50] & (|(KEYMGR_DPE_PERMIT[50] & ~reg_be))) | (addr_hit[51] & (|(KEYMGR_DPE_PERMIT[51] & ~reg_be))) | (addr_hit[52] & (|(KEYMGR_DPE_PERMIT[52] & ~reg_be))) | - (addr_hit[53] & (|(KEYMGR_DPE_PERMIT[53] & ~reg_be))))); + (addr_hit[53] & (|(KEYMGR_DPE_PERMIT[53] & ~reg_be))) | + (addr_hit[54] & (|(KEYMGR_DPE_PERMIT[54] & ~reg_be))) | + (addr_hit[55] & (|(KEYMGR_DPE_PERMIT[55] & ~reg_be))) | + (addr_hit[56] & (|(KEYMGR_DPE_PERMIT[56] & ~reg_be))) | + (addr_hit[57] & (|(KEYMGR_DPE_PERMIT[57] & ~reg_be))) | + (addr_hit[58] & (|(KEYMGR_DPE_PERMIT[58] & ~reg_be))) | + (addr_hit[59] & (|(KEYMGR_DPE_PERMIT[59] & ~reg_be))) | + (addr_hit[60] & (|(KEYMGR_DPE_PERMIT[60] & ~reg_be))) | + (addr_hit[61] & (|(KEYMGR_DPE_PERMIT[61] & ~reg_be))) | + (addr_hit[62] & (|(KEYMGR_DPE_PERMIT[62] & ~reg_be))) | + (addr_hit[63] & (|(KEYMGR_DPE_PERMIT[63] & ~reg_be))) | + (addr_hit[64] & (|(KEYMGR_DPE_PERMIT[64] & ~reg_be))) | + (addr_hit[65] & (|(KEYMGR_DPE_PERMIT[65] & ~reg_be))) | + (addr_hit[66] & (|(KEYMGR_DPE_PERMIT[66] & ~reg_be))) | + (addr_hit[67] & (|(KEYMGR_DPE_PERMIT[67] & ~reg_be))) | + (addr_hit[68] & (|(KEYMGR_DPE_PERMIT[68] & ~reg_be))) | + (addr_hit[69] & (|(KEYMGR_DPE_PERMIT[69] & ~reg_be))))); end // Generate write-enables @@ -3065,14 +3921,30 @@ module keymgr_dpe_reg_top ( assign op_status_we = addr_hit[49] & reg_we & !reg_error; assign op_status_wd = reg_wdata[1:0]; - assign err_code_we = addr_hit[50] & reg_we & !reg_error; + assign metadata_low_0_re = addr_hit[50] & reg_re & !reg_error; + assign metadata_low_1_re = addr_hit[51] & reg_re & !reg_error; + assign metadata_low_2_re = addr_hit[52] & reg_re & !reg_error; + assign metadata_low_3_re = addr_hit[53] & reg_re & !reg_error; + assign metadata_low_4_re = addr_hit[54] & reg_re & !reg_error; + assign metadata_low_5_re = addr_hit[55] & reg_re & !reg_error; + assign metadata_low_6_re = addr_hit[56] & reg_re & !reg_error; + assign metadata_low_7_re = addr_hit[57] & reg_re & !reg_error; + assign metadata_high_0_re = addr_hit[58] & reg_re & !reg_error; + assign metadata_high_1_re = addr_hit[59] & reg_re & !reg_error; + assign metadata_high_2_re = addr_hit[60] & reg_re & !reg_error; + assign metadata_high_3_re = addr_hit[61] & reg_re & !reg_error; + assign metadata_high_4_re = addr_hit[62] & reg_re & !reg_error; + assign metadata_high_5_re = addr_hit[63] & reg_re & !reg_error; + assign metadata_high_6_re = addr_hit[64] & reg_re & !reg_error; + assign metadata_high_7_re = addr_hit[65] & reg_re & !reg_error; + assign err_code_we = addr_hit[66] & reg_we & !reg_error; assign err_code_invalid_op_wd = reg_wdata[0]; assign err_code_invalid_kmac_input_wd = reg_wdata[1]; assign err_code_invalid_shadow_update_wd = reg_wdata[2]; - assign debug_we = addr_hit[52] & reg_we & !reg_error; + assign debug_we = addr_hit[68] & reg_we & !reg_error; assign debug_invalid_creator_seed_wd = reg_wdata[0]; @@ -3091,7 +3963,7 @@ module keymgr_dpe_reg_top ( assign debug_invalid_root_key_wd = reg_wdata[7]; assign debug_inactive_lc_en_wd = reg_wdata[8]; - assign load_key_lock_we = addr_hit[53] & reg_we & !reg_error; + assign load_key_lock_we = addr_hit[69] & reg_we & !reg_error; assign load_key_lock_wd = reg_wdata[0]; @@ -3147,10 +4019,26 @@ module keymgr_dpe_reg_top ( reg_we_check[47] = 1'b0; reg_we_check[48] = 1'b0; reg_we_check[49] = op_status_we; - reg_we_check[50] = err_code_we; + reg_we_check[50] = 1'b0; reg_we_check[51] = 1'b0; - reg_we_check[52] = debug_we; - reg_we_check[53] = load_key_lock_we; + reg_we_check[52] = 1'b0; + reg_we_check[53] = 1'b0; + reg_we_check[54] = 1'b0; + reg_we_check[55] = 1'b0; + reg_we_check[56] = 1'b0; + reg_we_check[57] = 1'b0; + reg_we_check[58] = 1'b0; + reg_we_check[59] = 1'b0; + reg_we_check[60] = 1'b0; + reg_we_check[61] = 1'b0; + reg_we_check[62] = 1'b0; + reg_we_check[63] = 1'b0; + reg_we_check[64] = 1'b0; + reg_we_check[65] = 1'b0; + reg_we_check[66] = err_code_we; + reg_we_check[67] = 1'b0; + reg_we_check[68] = debug_we; + reg_we_check[69] = load_key_lock_we; end // Read data return @@ -3365,12 +4253,108 @@ module keymgr_dpe_reg_top ( end addr_hit[50]: begin + reg_rdata_next[31:0] = metadata_low_0_qs; + end + + addr_hit[51]: begin + reg_rdata_next[31:0] = metadata_low_1_qs; + end + + addr_hit[52]: begin + reg_rdata_next[31:0] = metadata_low_2_qs; + end + + addr_hit[53]: begin + reg_rdata_next[31:0] = metadata_low_3_qs; + end + + addr_hit[54]: begin + reg_rdata_next[31:0] = metadata_low_4_qs; + end + + addr_hit[55]: begin + reg_rdata_next[31:0] = metadata_low_5_qs; + end + + addr_hit[56]: begin + reg_rdata_next[31:0] = metadata_low_6_qs; + end + + addr_hit[57]: begin + reg_rdata_next[31:0] = metadata_low_7_qs; + end + + addr_hit[58]: begin + reg_rdata_next[0] = metadata_high_0_valid_0_qs; + reg_rdata_next[2:1] = metadata_high_0_boot_stage_0_qs; + reg_rdata_next[3] = metadata_high_0_allow_child_policy_0_qs; + reg_rdata_next[4] = metadata_high_0_exportable_policy_0_qs; + reg_rdata_next[5] = metadata_high_0_retain_parent_policy_0_qs; + end + + addr_hit[59]: begin + reg_rdata_next[0] = metadata_high_1_valid_1_qs; + reg_rdata_next[2:1] = metadata_high_1_boot_stage_1_qs; + reg_rdata_next[3] = metadata_high_1_allow_child_policy_1_qs; + reg_rdata_next[4] = metadata_high_1_exportable_policy_1_qs; + reg_rdata_next[5] = metadata_high_1_retain_parent_policy_1_qs; + end + + addr_hit[60]: begin + reg_rdata_next[0] = metadata_high_2_valid_2_qs; + reg_rdata_next[2:1] = metadata_high_2_boot_stage_2_qs; + reg_rdata_next[3] = metadata_high_2_allow_child_policy_2_qs; + reg_rdata_next[4] = metadata_high_2_exportable_policy_2_qs; + reg_rdata_next[5] = metadata_high_2_retain_parent_policy_2_qs; + end + + addr_hit[61]: begin + reg_rdata_next[0] = metadata_high_3_valid_3_qs; + reg_rdata_next[2:1] = metadata_high_3_boot_stage_3_qs; + reg_rdata_next[3] = metadata_high_3_allow_child_policy_3_qs; + reg_rdata_next[4] = metadata_high_3_exportable_policy_3_qs; + reg_rdata_next[5] = metadata_high_3_retain_parent_policy_3_qs; + end + + addr_hit[62]: begin + reg_rdata_next[0] = metadata_high_4_valid_4_qs; + reg_rdata_next[2:1] = metadata_high_4_boot_stage_4_qs; + reg_rdata_next[3] = metadata_high_4_allow_child_policy_4_qs; + reg_rdata_next[4] = metadata_high_4_exportable_policy_4_qs; + reg_rdata_next[5] = metadata_high_4_retain_parent_policy_4_qs; + end + + addr_hit[63]: begin + reg_rdata_next[0] = metadata_high_5_valid_5_qs; + reg_rdata_next[2:1] = metadata_high_5_boot_stage_5_qs; + reg_rdata_next[3] = metadata_high_5_allow_child_policy_5_qs; + reg_rdata_next[4] = metadata_high_5_exportable_policy_5_qs; + reg_rdata_next[5] = metadata_high_5_retain_parent_policy_5_qs; + end + + addr_hit[64]: begin + reg_rdata_next[0] = metadata_high_6_valid_6_qs; + reg_rdata_next[2:1] = metadata_high_6_boot_stage_6_qs; + reg_rdata_next[3] = metadata_high_6_allow_child_policy_6_qs; + reg_rdata_next[4] = metadata_high_6_exportable_policy_6_qs; + reg_rdata_next[5] = metadata_high_6_retain_parent_policy_6_qs; + end + + addr_hit[65]: begin + reg_rdata_next[0] = metadata_high_7_valid_7_qs; + reg_rdata_next[2:1] = metadata_high_7_boot_stage_7_qs; + reg_rdata_next[3] = metadata_high_7_allow_child_policy_7_qs; + reg_rdata_next[4] = metadata_high_7_exportable_policy_7_qs; + reg_rdata_next[5] = metadata_high_7_retain_parent_policy_7_qs; + end + + addr_hit[66]: begin reg_rdata_next[0] = err_code_invalid_op_qs; reg_rdata_next[1] = err_code_invalid_kmac_input_qs; reg_rdata_next[2] = err_code_invalid_shadow_update_qs; end - addr_hit[51]: begin + addr_hit[67]: begin reg_rdata_next[0] = fault_status_cmd_qs; reg_rdata_next[1] = fault_status_kmac_fsm_qs; reg_rdata_next[2] = fault_status_kmac_done_qs; @@ -3387,7 +4371,7 @@ module keymgr_dpe_reg_top ( reg_rdata_next[13] = fault_status_key_ecc_qs; end - addr_hit[52]: begin + addr_hit[68]: begin reg_rdata_next[0] = debug_invalid_creator_seed_qs; reg_rdata_next[1] = debug_invalid_owner_seed_qs; reg_rdata_next[2] = debug_invalid_dev_id_qs; @@ -3399,7 +4383,7 @@ module keymgr_dpe_reg_top ( reg_rdata_next[8] = debug_inactive_lc_en_qs; end - addr_hit[53]: begin + addr_hit[69]: begin reg_rdata_next[0] = load_key_lock_qs; end diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 01b29069c87d9..11be3f8e6c975 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -12669,7 +12669,7 @@ { hart: 0x21140000 } - size_byte: 0x100 + size_byte: 0x200 } ] xbar: false diff --git a/hw/top_darjeeling/doc/memory_map.md b/hw/top_darjeeling/doc/memory_map.md index bb227e0883039..40a3c6f7f275f 100644 --- a/hw/top_darjeeling/doc/memory_map.md +++ b/hw/top_darjeeling/doc/memory_map.md @@ -39,7 +39,7 @@ The main address space, shared between the CPU and DM | hmac | default | `0x21110000` | `0x2000` | `0x800` | hmac | | kmac | default | `0x21120000` | `0x1000` | `0x400` | kmac | | otbn | default | `0x21130000` | `0x10000` | `0x4000` | otbn | -| keymgr_dpe | default | `0x21140000` | `0x100` | `0x40` | keymgr_dpe | +| keymgr_dpe | default | `0x21140000` | `0x200` | `0x80` | keymgr_dpe | | csrng | default | `0x21150000` | `0x80` | `0x20` | csrng | | entropy_src | default | `0x21160000` | `0x100` | `0x40` | entropy_src | | edn0 | default | `0x21170000` | `0x80` | `0x20` | edn0 | diff --git a/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv index d483d820df247..475bfef80ee48 100644 --- a/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv @@ -59,7 +59,7 @@ tl_device_t xbar_devices[$] = '{ '{32'h21130000, 32'h2113ffff} }}, '{"keymgr_dpe", '{ - '{32'h21140000, 32'h211400ff} + '{32'h21140000, 32'h211401ff} }}, '{"rv_core_ibex__cfg", '{ '{32'h211f0000, 32'h211f07ff} diff --git a/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg b/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg index 7312aa2303b14..6aa7e08469d24 100644 --- a/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg @@ -88,7 +88,7 @@ -node tb.dut*.u_otbn tl_*i.a_address[23:21] -node tb.dut*.u_otbn tl_*i.a_address[28:25] -node tb.dut*.u_otbn tl_*i.a_address[31:30] --node tb.dut*.u_keymgr_dpe tl_*i.a_address[17:8] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[17:9] -node tb.dut*.u_keymgr_dpe tl_*i.a_address[19:19] -node tb.dut*.u_keymgr_dpe tl_*i.a_address[23:21] -node tb.dut*.u_keymgr_dpe tl_*i.a_address[28:25] diff --git a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson index 63429908a96c8..c0194158051c9 100644 --- a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -624,7 +624,7 @@ { hart: 0x21140000 } - size_byte: 0x100 + size_byte: 0x200 } ] xbar: false diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg index 7760007fa5319..aefd77fc47894 100644 --- a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg @@ -86,7 +86,7 @@ -node tb.dut tl_otbn_o.a_address[23:21] -node tb.dut tl_otbn_o.a_address[28:25] -node tb.dut tl_otbn_o.a_address[31:30] --node tb.dut tl_keymgr_dpe_o.a_address[17:8] +-node tb.dut tl_keymgr_dpe_o.a_address[17:9] -node tb.dut tl_keymgr_dpe_o.a_address[19:19] -node tb.dut tl_keymgr_dpe_o.a_address[23:21] -node tb.dut tl_keymgr_dpe_o.a_address[28:25] diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv index f14988addcd10..24c93027beb83 100644 --- a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv @@ -62,7 +62,7 @@ tl_device_t xbar_devices[$] = '{ '{32'h21130000, 32'h2113ffff} }}, '{"keymgr_dpe", '{ - '{32'h21140000, 32'h211400ff} + '{32'h21140000, 32'h211401ff} }}, '{"rv_core_ibex__cfg", '{ '{32'h211f0000, 32'h211f07ff} diff --git a/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index 8a4fbf7350e7d..64e0caa41e3f1 100644 --- a/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv @@ -64,7 +64,7 @@ package tl_main_pkg; localparam logic [31:0] ADDR_MASK_EDN1 = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 07ffffff; localparam logic [31:0] ADDR_MASK_OTBN = 32'h 0000ffff; - localparam logic [31:0] ADDR_MASK_KEYMGR_DPE = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_KEYMGR_DPE = 32'h 000001ff; localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX__CFG = 32'h 000007ff; localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__REGS = 32'h 0000003f; localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__RAM = 32'h 0000ffff; diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv index cdf8d641062e4..11c5bb8372e27 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv @@ -267,7 +267,7 @@ package top_darjeeling_pkg; /** * Peripheral size in bytes for keymgr_dpe in top darjeeling. */ - parameter int unsigned TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES = 32'h100; + parameter int unsigned TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES = 32'h200; /** * Peripheral base address for csrng in top darjeeling. diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs index c05d27602c3ee..f36571e1bb434 100644 --- a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs +++ b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs @@ -383,7 +383,7 @@ pub const KEYMGR_DPE_BASE_ADDR: usize = 0x21140000; /// memory-mapped registers associated with this peripheral should have an /// address between #KEYMGR_DPE_BASE_ADDR and /// `KEYMGR_DPE_BASE_ADDR + KEYMGR_DPE_SIZE_BYTES`. -pub const KEYMGR_DPE_SIZE_BYTES: usize = 0x100; +pub const KEYMGR_DPE_SIZE_BYTES: usize = 0x200; /// Peripheral base address for csrng in top darjeeling. /// diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling.h b/hw/top_darjeeling/sw/autogen/top_darjeeling.h index 42dc1082e8f61..6504dbea382f0 100644 --- a/hw/top_darjeeling/sw/autogen/top_darjeeling.h +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling.h @@ -496,7 +496,7 @@ extern "C" { * address between #TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR and * `TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR + TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES`. */ -#define TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES 0x100u +#define TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES 0x200u /** * Peripheral base address for csrng in top darjeeling. diff --git a/hw/top_darjeeling/sw/autogen/top_memory.h b/hw/top_darjeeling/sw/autogen/top_memory.h index 6b34f32e1bb66..821e3ec7ae139 100644 --- a/hw/top_darjeeling/sw/autogen/top_memory.h +++ b/hw/top_darjeeling/sw/autogen/top_memory.h @@ -527,7 +527,7 @@ * address between #TOP_KEYMGR_DPE_BASE_ADDR and * `TOP_KEYMGR_DPE_BASE_ADDR + TOP_KEYMGR_DPE_SIZE_BYTES`. */ -#define TOP_KEYMGR_DPE_SIZE_BYTES 0x100 +#define TOP_KEYMGR_DPE_SIZE_BYTES 0x200 /** * Peripheral base address for csrng in top darjeeling. * diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 47dde62d65248..7c880a79d7ca7 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -11982,7 +11982,7 @@ { hart: 0x41140000 } - size_byte: 0x100 + size_byte: 0x200 } ] xbar: false diff --git a/hw/top_earlgrey/doc/memory_map.md b/hw/top_earlgrey/doc/memory_map.md index 14427378bf50e..8bfb4497ee0ca 100644 --- a/hw/top_earlgrey/doc/memory_map.md +++ b/hw/top_earlgrey/doc/memory_map.md @@ -49,7 +49,7 @@ The main address space, shared between the CPU and DM | hmac | default | `0x41110000` | `0x2000` | `0x800` | hmac | | kmac | default | `0x41120000` | `0x1000` | `0x400` | kmac | | otbn | default | `0x41130000` | `0x10000` | `0x4000` | otbn | -| keymgr_dpe | default | `0x41140000` | `0x100` | `0x40` | keymgr_dpe | +| keymgr_dpe | default | `0x41140000` | `0x200` | `0x80` | keymgr_dpe | | csrng | default | `0x41150000` | `0x80` | `0x20` | csrng | | entropy_src | default | `0x41160000` | `0x100` | `0x40` | entropy_src | | edn0 | default | `0x41170000` | `0x80` | `0x20` | edn0 | diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv index b27416cc44a18..c6cb87073cb87 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv @@ -65,7 +65,7 @@ tl_device_t xbar_devices[$] = '{ '{32'h41130000, 32'h4113ffff} }}, '{"keymgr_dpe", '{ - '{32'h41140000, 32'h411400ff} + '{32'h41140000, 32'h411401ff} }}, '{"rv_core_ibex__cfg", '{ '{32'h411f0000, 32'h411f00ff} diff --git a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg index 28b9f02091ecc..01e2b636a21fb 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg @@ -96,7 +96,7 @@ -node tb.dut*.u_otbn tl_*i.a_address[23:21] -node tb.dut*.u_otbn tl_*i.a_address[29:25] -node tb.dut*.u_otbn tl_*i.a_address[31:31] --node tb.dut*.u_keymgr_dpe tl_*i.a_address[17:8] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[17:9] -node tb.dut*.u_keymgr_dpe tl_*i.a_address[19:19] -node tb.dut*.u_keymgr_dpe tl_*i.a_address[23:21] -node tb.dut*.u_keymgr_dpe tl_*i.a_address[29:25] diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson index 6bd88e320c4a8..5518c4a1f30d3 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -633,7 +633,7 @@ { hart: 0x41140000 } - size_byte: 0x100 + size_byte: 0x200 } ] xbar: false diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg index ac93f7f1959be..7efc30fb8e4bc 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg @@ -94,7 +94,7 @@ -node tb.dut tl_otbn_o.a_address[23:21] -node tb.dut tl_otbn_o.a_address[29:25] -node tb.dut tl_otbn_o.a_address[31:31] --node tb.dut tl_keymgr_dpe_o.a_address[17:8] +-node tb.dut tl_keymgr_dpe_o.a_address[17:9] -node tb.dut tl_keymgr_dpe_o.a_address[19:19] -node tb.dut tl_keymgr_dpe_o.a_address[23:21] -node tb.dut tl_keymgr_dpe_o.a_address[29:25] diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv index ba7580bb3d134..0923b0fbb8301 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv @@ -69,7 +69,7 @@ tl_device_t xbar_devices[$] = '{ '{32'h41130000, 32'h4113ffff} }}, '{"keymgr_dpe", '{ - '{32'h41140000, 32'h411400ff} + '{32'h41140000, 32'h411401ff} }}, '{"rv_core_ibex__cfg", '{ '{32'h411f0000, 32'h411f00ff} diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index b7d4fee317167..e376c270fcb81 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv @@ -62,7 +62,7 @@ package tl_main_pkg; localparam logic [31:0] ADDR_MASK_EDN1 = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 07ffffff; localparam logic [31:0] ADDR_MASK_OTBN = 32'h 0000ffff; - localparam logic [31:0] ADDR_MASK_KEYMGR_DPE = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_KEYMGR_DPE = 32'h 000001ff; localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX__CFG = 32'h 000000ff; localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__REGS = 32'h 0000003f; localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__RAM = 32'h 0001ffff; diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index cf6f0bcad36ec..3ea3139dc3846 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv @@ -367,7 +367,7 @@ package top_earlgrey_pkg; /** * Peripheral size in bytes for keymgr_dpe in top earlgrey. */ - parameter int unsigned TOP_EARLGREY_KEYMGR_DPE_SIZE_BYTES = 32'h100; + parameter int unsigned TOP_EARLGREY_KEYMGR_DPE_SIZE_BYTES = 32'h200; /** * Peripheral base address for csrng in top earlgrey. diff --git a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs index 179f3f8ab02e4..5af78b280c95b 100644 --- a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs +++ b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs @@ -523,7 +523,7 @@ pub const KEYMGR_DPE_BASE_ADDR: usize = 0x41140000; /// memory-mapped registers associated with this peripheral should have an /// address between #KEYMGR_DPE_BASE_ADDR and /// `KEYMGR_DPE_BASE_ADDR + KEYMGR_DPE_SIZE_BYTES`. -pub const KEYMGR_DPE_SIZE_BYTES: usize = 0x100; +pub const KEYMGR_DPE_SIZE_BYTES: usize = 0x200; /// Peripheral base address for csrng in top earlgrey. /// diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index 3135c833920fd..fa6c5d24a647c 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h @@ -676,7 +676,7 @@ extern "C" { * address between #TOP_EARLGREY_KEYMGR_DPE_BASE_ADDR and * `TOP_EARLGREY_KEYMGR_DPE_BASE_ADDR + TOP_EARLGREY_KEYMGR_DPE_SIZE_BYTES`. */ -#define TOP_EARLGREY_KEYMGR_DPE_SIZE_BYTES 0x100u +#define TOP_EARLGREY_KEYMGR_DPE_SIZE_BYTES 0x200u /** * Peripheral base address for csrng in top earlgrey. diff --git a/hw/top_earlgrey/sw/autogen/top_memory.h b/hw/top_earlgrey/sw/autogen/top_memory.h index ef4c65de6a9df..dc95ca0cebaad 100644 --- a/hw/top_earlgrey/sw/autogen/top_memory.h +++ b/hw/top_earlgrey/sw/autogen/top_memory.h @@ -707,7 +707,7 @@ * address between #TOP_KEYMGR_DPE_BASE_ADDR and * `TOP_KEYMGR_DPE_BASE_ADDR + TOP_KEYMGR_DPE_SIZE_BYTES`. */ -#define TOP_KEYMGR_DPE_SIZE_BYTES 0x100 +#define TOP_KEYMGR_DPE_SIZE_BYTES 0x200 /** * Peripheral base address for csrng in top earlgrey. * From aff1de6a269e15ed5417b1cbf841b028519a1213 Mon Sep 17 00:00:00 2001 From: Raphael Roth Date: Thu, 3 Sep 2026 13:30:59 +0200 Subject: [PATCH 2/3] [keymgr_dpe, rtl] Connect metadata to the register Signed-off-by: Raphael Roth --- hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv | 26 +++++++++++++++++++------ hw/ip/keymgr_dpe/rtl/keymgr_dpe_ctrl.sv | 6 ++++++ hw/ip/keymgr_dpe/rtl/keymgr_dpe_pkg.sv | 20 +++++++++++++++++++ 3 files changed, 46 insertions(+), 6 deletions(-) diff --git a/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv b/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv index 7e5456b957386..52c292d75a2b7 100644 --- a/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv +++ b/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv @@ -289,13 +289,23 @@ module keymgr_dpe logic sideload_sel_err; logic key_version_vld; + keymgr_dpe_metadata_slot_t [NumInstHwSlot-1:0] metadata; for (genvar i = 0; i < NumMaxHwSlot; i++) begin : gen_metadata_read_data - assign hw2reg.metadata_high[i].valid.d = '0; - assign hw2reg.metadata_high[i].exportable_policy.d = '0; - assign hw2reg.metadata_high[i].retain_parent_policy.d = '0; - assign hw2reg.metadata_high[i].allow_child_policy.d = '0; - assign hw2reg.metadata_high[i].boot_stage.d = '0; - assign hw2reg.metadata_low[i].d = '0; + if (i < NumInstHwSlot) begin : gen_inst_slot + assign hw2reg.metadata_high[i].valid.d = metadata[i].valid; + assign hw2reg.metadata_high[i].exportable_policy.d = metadata[i].key_policy.exportable; + assign hw2reg.metadata_high[i].retain_parent_policy.d = metadata[i].key_policy.retain_parent; + assign hw2reg.metadata_high[i].allow_child_policy.d = metadata[i].key_policy.allow_child; + assign hw2reg.metadata_high[i].boot_stage.d = metadata[i].boot_stage; + assign hw2reg.metadata_low[i].d = metadata[i].max_key_version; + end else begin : gen_tieoff_slot + assign hw2reg.metadata_high[i].valid.d = '0; + assign hw2reg.metadata_high[i].exportable_policy.d = '0; + assign hw2reg.metadata_high[i].retain_parent_policy.d = '0; + assign hw2reg.metadata_high[i].allow_child_policy.d = '0; + assign hw2reg.metadata_high[i].boot_stage.d = '0; + assign hw2reg.metadata_low[i].d = '0; + end end for (genvar i = 0; i < Shares; i++) begin : gen_truncate_data @@ -372,6 +382,7 @@ module keymgr_dpe .max_key_version_i(reg2hw.max_key_ver_shadowed), .key_version_i(reg2hw.key_version), .key_version_vld_o(key_version_vld), + .metadata_o(metadata), .op_start_i(op_start), .op_done_o(op_done), .init_o(init), @@ -934,6 +945,9 @@ module keymgr_dpe // Verify supported number of boot stage `ASSERT_INIT(InvalidNumOfBootStage_A, NumBootStages inside {2, 3}) + // Verify the metadata do not exceed the width of the sw registers + `ASSERT_INIT(MetadataExceedSwReg_A, $bits(keymgr_dpe_metadata_slot_t) <= 2*top_pkg::TL_DW) + // Verify the number of instanciated HW slots `ASSERT_INIT(InvalidNumHwSlot_A, NumInstHwSlot <= NumMaxHwSlot) // Only a power-of-two for the NumInstHwSlot is supported diff --git a/hw/ip/keymgr_dpe/rtl/keymgr_dpe_ctrl.sv b/hw/ip/keymgr_dpe/rtl/keymgr_dpe_ctrl.sv index 8a44e5368a56f..de1a245d27a4a 100644 --- a/hw/ip/keymgr_dpe/rtl/keymgr_dpe_ctrl.sv +++ b/hw/ip/keymgr_dpe/rtl/keymgr_dpe_ctrl.sv @@ -45,6 +45,7 @@ module keymgr_dpe_ctrl input [KeyVersionWidth-1:0] max_key_version_i, input [KeyVersionWidth-1:0] key_version_i, output key_version_vld_o, + output keymgr_dpe_metadata_slot_t [NumInstHwSlot-1:0] metadata_o, output logic op_done_o, output keymgr_dpe_op_status_e status_o, @@ -140,6 +141,11 @@ module keymgr_dpe_ctrl assign gen_hw_key_cmd = op_start_i & (op_i == OpDpeGenHwOut) & en_i; assign disable_cmd = op_start_i & (op_i == OpDpeDisable) & en_i; + // Forward all metadata to the sw register + for (genvar i = 0; i < NumInstHwSlot; i++) begin : gen_metadata_output + assign metadata_o[i] = extract_metadata_from_slot(key_slots_q[i]); + end + /////////////////////////// // interaction between main control fsm and operation fsm /////////////////////////// diff --git a/hw/ip/keymgr_dpe/rtl/keymgr_dpe_pkg.sv b/hw/ip/keymgr_dpe/rtl/keymgr_dpe_pkg.sv index 4144f1e1764b3..9d4d84c4aba9e 100644 --- a/hw/ip/keymgr_dpe/rtl/keymgr_dpe_pkg.sv +++ b/hw/ip/keymgr_dpe/rtl/keymgr_dpe_pkg.sv @@ -262,6 +262,14 @@ package keymgr_dpe_pkg; keymgr_dpe_policy_t key_policy; } keymgr_dpe_slot_t; + // Internal metadata for each slot + typedef struct packed { + keymgr_dpe_policy_t key_policy; + keymgr_dpe_boot_stage_e boot_stage; + logic valid; + logic [KeyVersionWidth-1:0] max_key_version; + } keymgr_dpe_metadata_slot_t; + typedef enum logic [2:0] { SlotUpdateIdle, SlotDestRandomize, @@ -406,4 +414,16 @@ package keymgr_dpe_pkg; return |value & ~&value; endfunction + // extract all metadata from a slot + function automatic keymgr_dpe_metadata_slot_t extract_metadata_from_slot (keymgr_dpe_slot_t slot); + // read unused signal to avoid linter warnings + logic [Shares-1:0][KeyWidth-1:0] unused_key = slot.key; + return keymgr_dpe_metadata_slot_t'{ + slot.key_policy, + slot.boot_stage, + slot.valid, + slot.max_key_version + }; + endfunction + endpackage : keymgr_dpe_pkg From 7b8893b244458e54d0ed72ba1216d53d61e26f6a Mon Sep 17 00:00:00 2001 From: Raphael Roth Date: Thu, 3 Sep 2026 13:43:57 +0200 Subject: [PATCH 3/3] [keymgr_dpe, doc] Document `METADATA` registers Signed-off-by: Raphael Roth --- hw/ip/keymgr_dpe/doc/programmers_guide.md | 13 +++++++++++++ hw/ip/keymgr_dpe/doc/theory_of_operation.md | 4 ++++ 2 files changed, 17 insertions(+) diff --git a/hw/ip/keymgr_dpe/doc/programmers_guide.md b/hw/ip/keymgr_dpe/doc/programmers_guide.md index 6fa0d7f570c23..b0538e8f83486 100644 --- a/hw/ip/keymgr_dpe/doc/programmers_guide.md +++ b/hw/ip/keymgr_dpe/doc/programmers_guide.md @@ -77,6 +77,19 @@ SW needs to configure the following registers to erase a slot: At the end of a successful erase operation, the secret of the destination slot is removed and the slot is marked as invalid. +## Read Slot Metadata + +Software can read back a slot's `valid`, `boot_stage`, `max_key_version` and `key_policy` fields at any time by reading the `METADATA_LOW` and `METADATA_HIGH` registers at the corresponding slot index: +* `METADATA_LOW[i].MAX_KEY_VERSION` reports `max_key_version` of slot `i`. +* `METADATA_HIGH[i].VALID` reports whether slot `i` currently holds a valid DPE context. +* `METADATA_HIGH[i].BOOT_STAGE` reports the `boot_stage` of slot `i`. +* `METADATA_HIGH[i].ALLOW_CHILD_POLICY` reports the `allow_child` policy applied to slot `i`. +* `METADATA_HIGH[i].EXPORTABLE_POLICY` reports the `exportable` policy applied to slot `i`. +* `METADATA_HIGH[i].RETAIN_PARENT_POLICY` reports the `retain_parent` policy applied to slot `i`. + +The secret key itself is never exposed through these registers. +Both registers are replicated `NumMaxHwSlot` times but only indices below `NumInstHwSlot` correspond to an actual hardware slot, the remaining slots are bound to `0`. + # Disable SW needs to configure the following registers to disable keymgr_dpe: diff --git a/hw/ip/keymgr_dpe/doc/theory_of_operation.md b/hw/ip/keymgr_dpe/doc/theory_of_operation.md index ecd8f3bd6c21d..bd53db91fd7c8 100644 --- a/hw/ip/keymgr_dpe/doc/theory_of_operation.md +++ b/hw/ip/keymgr_dpe/doc/theory_of_operation.md @@ -60,6 +60,10 @@ Otherwise all advance requests are rejected that specify this slot as its source * If `retain_parent` is set to `true`/`1`, then the parent slot remains valid after an advance call. Otherwise, after the derivation of a child slot, the DPE context of the parent slot is removed automatically. +With the exception of the secret key itself, software can read back a slot's `valid`, `boot_stage`, `max_key_version` and `key_policy` subfields at any time through the `METADATA_LOW` and `METADATA_HIGH` registers. +Both registers are replicated `NumMaxHwSlot` times but only indices below `NumInstHwSlot` correspond to an actual hardware slot, the remaining slots are bound to `0`. +`METADATA_LOW.MAX_KEY_VERSION` reports `max_key_version`, while `METADATA_HIGH` reports `valid`, `boot_stage` and `key_policy` subfields respectively. + ## Key Manager State The key manager working state represents the current working state of the key manager and it is decoupled from the DICE hierarchy.