From 54fea7f44da19f3640d9d7cbfde4df7561412ec0 Mon Sep 17 00:00:00 2001 From: tchilikov-semify Date: Fri, 11 Sep 2026 15:26:43 +0100 Subject: [PATCH] [rv_plic] add missing output known assertion Add ASSERT_KNOWN to alert_tx_o. --- hw/top_chip/ip_autogen/rv_plic/rtl/rv_plic.sv | 1 + .../ip_templates/rv_plic/rtl/rv_plic.sv.tpl | 1 + .../rv_plic/0002_Add_Missing_Output_Assertion.patch | 12 ++++++++++++ 3 files changed, 14 insertions(+) create mode 100644 hw/vendor/patches/lowrisc_ip/rv_plic/0002_Add_Missing_Output_Assertion.patch diff --git a/hw/top_chip/ip_autogen/rv_plic/rtl/rv_plic.sv b/hw/top_chip/ip_autogen/rv_plic/rtl/rv_plic.sv index 89a98716e..9e9c84336 100644 --- a/hw/top_chip/ip_autogen/rv_plic/rtl/rv_plic.sv +++ b/hw/top_chip/ip_autogen/rv_plic/rtl/rv_plic.sv @@ -276,6 +276,7 @@ module rv_plic import rv_plic_reg_pkg::*; #( // Assertions `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) + `ASSERT_KNOWN(AlertKnownO_A, alert_tx_o) `ASSERT_KNOWN(IrqKnownO_A, irq_o) `ASSERT_KNOWN(MsipKnownO_A, msip_o) for (genvar k = 0; k < NumTarget; k++) begin : gen_irq_id_known diff --git a/hw/vendor/lowrisc_ip/ip_templates/rv_plic/rtl/rv_plic.sv.tpl b/hw/vendor/lowrisc_ip/ip_templates/rv_plic/rtl/rv_plic.sv.tpl index 9f2cc636a..d8b830947 100644 --- a/hw/vendor/lowrisc_ip/ip_templates/rv_plic/rtl/rv_plic.sv.tpl +++ b/hw/vendor/lowrisc_ip/ip_templates/rv_plic/rtl/rv_plic.sv.tpl @@ -273,6 +273,7 @@ module ${module_instance_name} import ${module_instance_name}_reg_pkg::*; #( % if racl_support: `ASSERT_KNOWN(RaclErrorValidKnown_A, racl_error_o.valid) % endif + `ASSERT_KNOWN(AlertKnownO_A, alert_tx_o) `ASSERT_KNOWN(IrqKnownO_A, irq_o) `ASSERT_KNOWN(MsipKnownO_A, msip_o) for (genvar k = 0; k < NumTarget; k++) begin : gen_irq_id_known diff --git a/hw/vendor/patches/lowrisc_ip/rv_plic/0002_Add_Missing_Output_Assertion.patch b/hw/vendor/patches/lowrisc_ip/rv_plic/0002_Add_Missing_Output_Assertion.patch new file mode 100644 index 000000000..2a90ed6b7 --- /dev/null +++ b/hw/vendor/patches/lowrisc_ip/rv_plic/0002_Add_Missing_Output_Assertion.patch @@ -0,0 +1,12 @@ +diff --git a/rtl/rv_plic.sv.tpl b/rtl/rv_plic.sv.tpl +index 9f2cc636..d8b83094 100644 +--- a/rtl/rv_plic.sv.tpl ++++ b/rtl/rv_plic.sv.tpl +@@ -273,6 +273,7 @@ module ${module_instance_name} import ${module_instance_name}_reg_pkg::*; #( + % if racl_support: + `ASSERT_KNOWN(RaclErrorValidKnown_A, racl_error_o.valid) + % endif ++ `ASSERT_KNOWN(AlertKnownO_A, alert_tx_o) + `ASSERT_KNOWN(IrqKnownO_A, irq_o) + `ASSERT_KNOWN(MsipKnownO_A, msip_o) + for (genvar k = 0; k < NumTarget; k++) begin : gen_irq_id_known